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UCIe 4.0 Specification Released, Extending Chiplet Interconnect to System-Level Integration

Source: IT之家 Published: Developers 中文 LaunchUCIe
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The UCIe Consortium released version 4.0 of its chiplet interconnect specification on the 12th local time. The latest iteration extends the UCIe architecture from chip-level interface design to address key requirements for integrating multiple chips into a unified package system. UCIe 4.0 introduces a standard on-package memory link, with the UCIe.mem protocol simplifying integration between SoCs and memory logic dies, achieving up to 93.75% data efficiency and approximately 2.5 TB/s/mm of die-edge bandwidth density; new power-optimized profiles deliver 30–80% energy efficiency gains at 64GT/s; and an enhanced bump design for standard-package UCIe improves area efficiency. In addition, UCIe 4.0 includes features that enhance system-level security and manageability, including trusted chip state reporting and a bidirectional integrity-protected management channel; it also extends the system-level reliability of UCIe interconnect for automotive application scenarios.

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UCIe 4.0 Specification Released, Extending Chiplet Interconnect to System-Level Integration

IT Home, November 13 news: The UCIe Consortium local time on the 12th released version 4.0 of the chiplet interconnect specification. The latest iteration extends the UCIe architecture from chip-level interface design to meet the key requirements for integrating multiple chips into a unified package system.

UCIe 4.0 introduces a standard on-die memory link. The UCIe.mem protocol simplifies integration between the SoC and memory logic dies, achieving data efficiency of up to 93.75% and a beachfront bandwidth density of about 2.5 TB/s/mm; the new power-optimized profile delivers 30–80% energy efficiency improvements at 64GT/s; and the enhanced bump design for standard package UCIe improves area efficiency.

In addition, UCIe 4.0 includes a series of features that improve system-level security and manageability, including trusted chip status reporting and a bidirectional integrity-protected management channel; it also extends the system-level reliability of UCIe interconnect in automotive application scenarios.

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