Newshot
Account

Axelera AI unveils architecture for its data-center-class AIPU chip Titania, with production set for 2027Q3

Source: IT之家 Published: AI 中文 AIAIPUTitania
AI summary

Dutch chip startup Axelera AI on the 12th local time unveiled the architecture of Titania, its third-generation AIPU chip, aimed at the data center inference market; mass production is expected in Q3 2027, and it has already secured over $300 million in orders. The 400W chip consists of two compute chiplets based on the third-generation D-IMC architecture, is optimized for sparse MoE models, supports MXPF4 and MXFP8 data formats, delivers up to 2.5 PFLOPS of FP8 compute, and integrates 128MB of shared on-chip SRAM. It embeds 32 RISC-V cores to offload host CPU workloads, includes AV1, H.265 and other multi-format codecs, and its SiP integrates 128GB of LPDDR6 memory with 2456GB/s total bandwidth; at a higher level, Titania supports PCIe AIC and OCP OAM form factors, and a 4U eight-card air-cooled Titania server can run a 1.6T MoE model locally at FP4 precision. Axelera AI says Titania is expected to achieve 7x the throughput per watt and 1/20 the total cost of ownership of current data-center-class servers, and that the 4U air-cooled Titania server's per-user speed on DeepSeek R1 is enough to match NVIDIA's Vera Rubin NVL72 liquid-cooled rack.

Translation(model translation, not the source's own text)

Axelera AI Unveils Architecture of Data Center-Class AIPU Chip Titania, Production Slated for 2027Q3

IT之家 news, November 13: Netherlands-based chip startup Axelera AI on the 12th local time unveiled the architecture of Titania, its third-generation AIPU chip. Targeting the data center inference market, it is expected to enter mass production in Q3 2027 and has already secured over $300 million (IT之家 note: roughly RMB 2.006 billion at current exchange rates) in orders.

The Titania chip has a design power of 400W and consists of 2 compute chiplets based on the third-generation D-IMC architecture. Optimized for sparse MoE models, it supports the MXPF4 and MXFP8 data formats, delivers up to 2.5PFLOPS of FP8 compute, and integrates 128MB of shared on-chip SRAM cache.

In addition, Titania embeds 32 RISC-V cores that can offload workloads from the host CPU; it also features multi-format codecs including AV1 and H.265; the SiP integrates 128GB of LPDDR6 memory with a total bandwidth of 2456GB/s.

At a higher level, Titania supports PCIe AIC and OCP OAM form factors; a single 4U eight-card Titania air-cooled server can run a 1.6T MoE model locally at FP4 precision.

Axelera AI says Titania is expected to achieve 7x the throughput per watt of current data center-class servers at 1/20 of the total cost of ownership. A 4U Titania air-cooled server's per-user speed on DeepSeek R1 is enough to match NVIDIA's Vera Rubin NVL72 liquid-cooled rack.

Related articles

  • South Korea unveils on-device AI semiconductor roadmap, plans to complete development and verification of 10 chips by 2030
  • UK AI chip startup Fractile wins government funding, valuation reaches $7 billion
  • AI data centers crowd out mature-node capacity, automotive chip supply chain faces bottlenecks
  • DEEPX 2nm low-power AI chip DX-M2 physical chip expected to arrive in early 2027
  • Chip stocks "bloodbath": US stocks endure roller-coaster plunge as Nasdaq wipes out post-2026 midterm election gains in 6 minutes
  • Korean chip startup FuriosaAI takes on 英伟达: valuation quadruples to $2.9 billion after new funding round

The translation is machine-generated and individual terms may be off. Nothing is rewritten or cut; the original is authoritative.

Published by IT之家
This site only summarises and aggregates; copyright stays with the original author. Headlines and summaries follow the source — where they differ, the original wins.
Read the original ↗