Newshot World's First: Single Matrix Equation Solve Time Under 100 Nanoseconds, Domestic Analog Computing Chip Unveiled
IT Home, November 15 news — According to Science and Technology Daily, learning from analog computing chip company Anna Zhixin, the company's self-developed AX100 chip completed tape-out in October. This is the world's first fully integrated analog computing chip that solves matrix equations in a single step.
Testing shows that the chip's single matrix equation solve time is less than 100 nanoseconds, with power consumption per computation of approximately 80 milliwatts, fully meeting theoretical simulation and design expectations.
According to the introduction, the AI large-model training parameter optimization, robot motion control and spatial planning, and communication base station signal processing that we are familiar with are all essentially solving complex matrix equations. The approach of digital chips is to transform "solving" into massive multiply-add iterations, with computational load growing cubically with matrix size — taking the solution of a 512-order matrix equation as an example, approximately 500 million multiply-adds are required, taking tens to hundreds of microseconds. Analog computing, by contrast, directly leverages physical laws to achieve parallel computation, with low latency and low power consumption, giving it inherent advantages against the backdrop of computing power bottlenecks. Anna Zhixin CEO Xiang Rui said, "The matrix equation is directly mapped to a circuit; after the circuit self-balances, the result is read out once, with no iteration needed."
How to make analog computing both reliable and scalable, so that it can leverage its inherent advantages in modern computing tasks, is a century-old challenge that has plagued the global scientific community. In October 2025, Sun Zhong's team, a researcher at the Institute for Artificial Intelligence at Peking University, published a paper in Nature Electronics, raising the precision of analog computing from the previous order of one percent to the order of one part in ten million. At the time, some scholars commented that Sun Zhong's research "revived" the long-neglected field of analog computing.
Only one year has passed since the paper was officially published, and thanks to China's mature chip manufacturing and packaging industry chain, Anna Zhixin has pushed Sun Zhong's team's technology from the laboratory to the production line.
The team has tested the chip in three scenarios. For large-model training, the team conducted validation on a 293-million-parameter Autoencoder model and a 272-million-parameter Transformer model; in the corresponding experiments, the second-order optimization scheme adopted reduced the training update cost of the two types of models by 92% and 56%, respectively. In the field of embodied intelligence, the chip can enhance robots' real-time computing capability, speeding up end-to-end algorithms for motion control and planning by 150% to 500%, and speeding up core algorithm stages of 3D reconstruction and SLAM (simultaneous localization and mapping) by 200% to 500%. In the field of wireless communications, evaluation results show that for a 128×128 channel Gram matrix, the analog computing chip achieves an equivalent throughput improvement of 20 to 207 times compared with existing digital ASIC chips and GPUs, and an equivalent energy efficiency improvement of 27.6 to 61.3 times.
IT Home has learned that the chip's manufacturing does not depend on advanced process nodes, and full-chain autonomous controllability can be achieved using currently mature processes.
"The AX100 chip and GPU-type digital chips are completely different in architecture and underlying logic, and it possesses top-tier computing capability among modern analog computing, and is expected to achieve 'overtaking on a new path' in the chip field," said Xiang Rui. This is the first time a Chinese company has the opportunity to participate in defining an important computing paradigm, and it will provide brand-new and more efficient underlying computing hardware for the widespread demand for matrix equation solving.
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