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Huawei Kirin 9050 Series' New-Generation Lingxi CPU Details Revealed: 9 Cores, 16 Threads with Parallel Scheduling, Supports Memory Compression Acceleration

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On November 13, ITHome reported that Huawei's official Kirin WeChat account disclosed more configuration details of the Kirin 9050 series — the first τ chip featuring "logic folding" technology — including the new-generation Lingxi CPU. The CPU supports 9-core, 16-thread hyper-threading, with 23% higher multi-core performance, 40% higher GPU rendering performance and 140% higher NPU performance; heavy-load scenarios (app launches, large file loading, gaming) are handled by 1 super-large core plus 2 performance large cores, multi-tasking scenarios (UX interaction, floating windows, video calls, split-screen) by 4 efficiency large cores, and daily scenarios (news browsing, short videos) by 2 small cores. The Kirin 9050 series also supports a memory compression accelerator with a 45% higher compression ratio and an average of 3GB more available memory, while intelligent heterogeneous scheduling improves battery life and hardened low-latency scheduling makes XPU collaboration more efficient.

Translation(model translation, not the source's own text)

Detailed Information on Huawei Kirin 9050 Series' New-Generation Lingxi CPU Revealed: 9 Cores, 16 Threads with Parallel Scheduling, Memory Compression Acceleration Support

IT Home, November 13 news — Huawei Kirin's official WeChat account has continued to reveal more configuration details of the Kirin 9050 series, the first τ chip with "logic folding" technology, and full details of the new-generation Lingxi CPU are now public.

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According to the introduction, the Kirin 9050 series is equipped with the new-generation Lingxi CPU, supporting 9-core, 16-thread hyper-threading technology, with multi-core performance improved by 23%, GPU rendering performance improved by 40%, and NPU performance improved by 140%. Combined with HarmonyOS application parallelization and intelligent scheduling, multitasking is smoother.

Heavy-load scenarios (app launches, large file loading, gaming) are handled by 1 super-large core + 2 performance large cores; multitasking scenarios (UX interaction, floating windows, video calls, split screen) are handled by 4 efficiency large cores; everyday scenarios (browsing news, short videos) are handled by 2 small cores.

In addition, the Kirin 9050 series chips also support a memory compression accelerator, with compression rate increased by 45% and available memory increased by an average of 3GB, making background multitasking more comfortable; intelligent heterogeneous scheduling can improve device battery life, and hardened low-latency scheduling makes XPU collaboration more efficient.

As IT Home previously reported, at Huawei's 2026 Kirin media communication event held in October this year, 徐松余, Director of the Wireless Terminal Chip Product Management Department of Huawei's Semiconductor Business, said that the Kirin 9050 series, as the first logic-folding τ chip, will embark on a new journey for the next 10 years. The PPT showed that Huawei aims to achieve a P-core frequency breakthrough of 5GHz by 2031.

The translation is machine-generated and individual terms may be off. Nothing is rewritten or cut; the original is authoritative.

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